1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, more particularly, to the manufacture of field effect transistors on the basis of stressed dielectric layers formed above the transistors, such as stressed contact etch stop layers used for generating a different type of strain in channel regions of different transistor types.
2. Description of the Related Art
Integrated circuits are typically comprised of a large number of circuit elements located on a given chip area according to a specified circuit layout, wherein, in complex circuits, the field effect transistor represents one predominant circuit element. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry based on field effect transistors, such as microprocessors, storage chips and the like, CMOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region.
The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the majority charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially determines the performance of the MOS transistors. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, renders the channel length a dominant design criteria for accomplishing an increase in the operating speed of the integrated circuits.
The shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. One issue associated with reduced gate lengths is the occurrence of so-called short channel effects, which may result in a reduced controllability of the channel conductivity. Short channel effects may be countered by certain design techniques, some of which, however, may be accompanied by a reduction of the channel conductivity, thereby partially offsetting the advantages obtained by the reduction of critical dimensions.
In view of this situation, it has been proposed to enhance device performance of the transistor elements not only by reducing the transistor dimensions but also by increasing the charge carrier mobility in the channel region for a given channel length, thereby increasing the drive current capability and thus transistor performance. For example, the lattice structure in the channel region may be modified, for instance by creating tensile or compressive strain therein, which results in a modified mobility for electrons and holes, respectively. For example, creating tensile strain in the channel region of a silicon layer having a standard crystallographic configuration may increase the mobility of electrons, which in turn may directly translate into a corresponding increase of the conductivity of N-type transistors. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors.
One promising approach in this respect is a technique that enables the creation of desired stress conditions within the channel region of different transistor elements by adjusting the stress characteristics of a contact etch stop layer that is formed above the basic transistor structure in order to form contact openings to the gate and drain and source terminals in an interlayer dielectric material. The effective control of mechanical stress in the channel region, i.e., effective stress engineering, may be accomplished by individually adjusting the internal stress in the contact etch stop layer of the respective transistor in order to position a contact etch stop layer having an internal compressive stress above a P-channel transistor while positioning a contact etch stop layer having an internal tensile strain above an N-channel transistor, thereby creating compressive and tensile strain, respectively, in the respective channel regions.
Typically, the contact etch stop layer is formed by plasma enhanced chemical vapor deposition (PECVD) processes above the transistor, i.e., above the gate structure and the drain and source regions, wherein, for instance, silicon nitride may be used due to its high etch selectivity with respect to silicon dioxide, which is a well-established interlayer dielectric material. Furthermore, PECVD silicon nitride may be deposited with a high intrinsic stress, for example, up to 2 Giga Pascal (GPa) or significantly higher of compressive stress and up to 1 GPa and significantly higher of tensile stress, wherein the type and the magnitude of the intrinsic stress may be efficiently adjusted by selecting appropriate deposition parameters. For example, ion bombardment, deposition pressure, substrate temperature, gas components and the like represent respective parameters that may be used for obtaining the desired intrinsic stress.
During the formation of the two types of stressed layers, conventional techniques may suffer from reduced efficiency when device dimensions are increasingly scaled using the 65 nm technology and even further advanced approaches, as will be explained in more detail with reference to FIGS. 1a-1c. 
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 in a certain manufacturing stage for forming stress-inducing layers above a first device area 110 and a second device area 120. The first and second device areas 110, 120 which typically represent respective transistor elements may be formed above a substrate 101 comprising a semiconductor layer 102, such as a silicon-based layer, which may be separated from the substrate 101 by an appropriate buried insulating layer if a silicon-on-insulator (SOI) configuration is considered. In the example shown, the second device area 120 may comprise a plurality of transistor elements, while only a single transistor is illustrated in the first device region 110. The transistors in the second device region 120 may comprise a gate electrode 121 formed on respective gate insulation layers 123, which separates the gate electrode 121 from a corresponding channel region 124, which is laterally located between respective drain/source regions 125. Furthermore, a sidewall spacer structure 122 may be formed on sidewalls of the gate electrode 121. Typically, metal silicide regions (not shown) may be provided in the drain and source regions 125 and the gate electrodes 121 in order to enhance the conductivity of these areas. The semiconductor device 100 may represent an advanced device, in which critical dimensions, such as the gate length, i.e., in FIG. 1a the horizontal extension of the gate electrodes 121, may be approximately 50 nm or significantly less. Consequently, a distance between respective transistor elements, i.e., the lateral distance between neighboring sidewall spacer structures 122 of closely spaced transistor elements, may be approximately 100 nm or even less, wherein, depending on the device configuration, in dense device areas, a plurality of closely spaced circuit elements may be provided.
In the first device region 110, the respective transistor element may have a similar configuration and may represent a transistor of a different conductivity type compared to the transistors in the second device region 120, depending on the device requirements. Thus, a respective gate electrode 111 formed on a gate insulation layer 113, separating the gate electrode 111 from a channel region 114, may be provided. A spacer sidewall structure 112 may be formed on sidewalls of the gate electrode 111, and respective drain/source regions 115 may be formed in the semiconductor layer 102. It should be appreciated that the first and second device regions 110, 120 may be separated by an appropriate isolation structure (not shown) if required. Furthermore, in the manufacturing stage shown in FIG. 1a, a silicon nitride layer 130 comprising a high intrinsic stress may be formed above the first and second device regions 110, 120 followed by an etch indicator layer 131 comprised of silicon dioxide. It should be appreciated that, if required, an etch stop layer (not shown), such as a silicon dioxide layer of appropriate thickness and density, may be provided between the silicon nitride layer 130 and the respective transistor elements in the first and second device regions 110, 120.
As is evident from FIG. 1a, due to the reduced spacing between neighboring transistor elements, as is for instance shown in the second device area 120, the silicon nitride layer 130 may define a respective surface topography in which tapered recesses, also referred to as seams 131, may be formed between the closely spaced transistor elements, since the spacing between the transistor elements may be on the order of two times a layer thickness of the silicon nitride layer 130. Thus, due to the pronounced surface topography at the seam 131, the silicon dioxide layer 132 may have a significantly increased thickness at this area due to locally different deposition conditions compared to other areas, which may result in significant etch non-uniformities, as will be described with reference to FIG. 1b. 
Furthermore, in this manufacturing stage, the semiconductor device 100 may comprise a resist mask 103 exposing the second device region 120, while covering the first device region 110. In this case, it may be assumed that the intrinsic stress of the silicon nitride layer 130 may be appropriately selected so as to enhance the transistor performance in the first device region 110.
A typical process flow for forming the semiconductor device 100 as shown in FIG. 1a may comprise the following processes. The gate electrodes 121, 111 and the gate insulation layers 123, 113 may be formed and patterned on the basis of well-established process techniques including advanced photolithography, deposition, oxidation and etch techniques. Thereafter, the drain and source regions 125, 115 may be formed in combination with the sidewall spacer structures 122, 112 on the basis of well-established deposition, anisotropic etch processes and implantation sequences in order to establish the desired vertical and lateral dopant profile. Thereafter, respective silicide regions (not shown) may be formed, if required, on the basis of well-established techniques. Thereafter, if required, a corresponding silicon dioxide etch stop layer (not shown) may be formed followed by the deposition of the silicon nitride layer 130. During the deposition of the silicon nitride material, respective process parameters, such as composition of carrier gases and reactive gases, substrate temperature, deposition pressure and, in particular, ion bombardment during the deposition, may significantly influence the finally obtained intrinsic stress of the material as deposited with respect to the underlying materials. Thus, by selecting appropriate parameter values, a high degree of intrinsic stress, such as up to 2 Giga Pascal (GPa) and even more of compressive stress or up to 1 GPa or even significantly higher of tensile stress, may be created so as to enhance the performance of the transistor in the first device region 110. Due to the less pronounced conformality of the silicon nitride deposition process and due to the reduced distance between the neighboring transistor elements in densely packed device areas, such as the second device region 120, the silicon nitride material may merge in the lateral growth direction between closely spaced transistor elements, thereby forming the respective seam 131. Thus, in the subsequent deposition of the silicon dioxide layer 132, the local deposition conditions at the seam 131 may result in a non-uniformity of the layer thickness, thereby creating a locally, significantly enhanced silicon dioxide thickness, which may even amount to a thickness of up to three to four times the thickness of the silicon dioxide layer 132 at areas distant from the seam 131.
After the deposition of the silicon dioxide layer 132, the resist mask 103 may be formed on the basis of well-established photolithography techniques. Next, an appropriately designed etch process may be performed in order to remove a portion of the layers 130 and 132 from the second device region 120. During the corresponding etch process, the silicon dioxide material of the layer 132 may be removed first, followed by a selective etch process for removing the material of the silicon nitride layer 130, wherein the corresponding etch process may be controlled on the basis of an etch stop layer, if required. Due to the significantly increased layer thickness of the silicon dioxide layer 132 at the seam 131, the material may not be completely removed during the etch process when removing the layer 132, thereby significantly blocking the selective etch chemistry during the subsequent etch process for removing the exposed portion of the silicon nitride layer 130.
FIG. 1b schematically illustrates the semiconductor device 100 after the corresponding etch process. Hence, after removal of the resist mask 103, the silicon nitride layer 130 may be formed above the first device region 110 including the silicon dioxide layer 132, while the corresponding transistor elements in the second device regions 120 are substantially exposed, except for respective material residues 133 caused by respective non-uniformities of the preceding etch process at the seam 131, as previously explained. During the further processing, i.e., the deposition of a silicon nitride layer having a different intrinsic stress above the first and second device areas 110, 120 and removing the corresponding silicon nitride layer from the first device region 110 by an etch process controlled on the basis of the etch indicator layer 132, the residues 133 may result in significant process non-uniformities, creating respective material residues when forming a contact opening at the seam 131, which may finally result in a reduced transistor performance or even a contact failure. Consequently, in sophisticated applications, the conventional process sequence for providing silicon nitride layers of different intrinsic stress may no longer be appropriate, in particular when transistor dimensions are further scaled down.
FIG. 1c schematically illustrates the semiconductor device 100 in an advanced manufacturing stage in order to demonstrate further issues associated with the conventional process sequence for forming silicon nitride layers of different intrinsic stress. In this manufacturing stage, the device region 110 may comprise a silicon nitride layer 130 and the silicon dioxide layer 132, while the transistors of the second device region 120 have formed thereabove a second silicon nitride layer 140 having a different type of intrinsic stress. Moreover, an interlayer dielectric material, such as a silicon dioxide material 150, may be provided followed by a respective resist mask 106 in order to define respective openings for forming a contact opening 151 in the interlayer dielectric material 150. The second silicon nitride layer 140 may be formed on the basis of an appropriately controlled deposition process, as previously described, followed by an etch process for removing the layer 140 from above the first device region 110, controlled by the etch indicator layer 132 in order to identify the end of the corresponding etch process. That is, during etching of the non-covered material of the layer 140 above the first device region 110, the etch front may finally reach the etch indicator layer 132, thereby releasing a certain degree of byproducts into the etch ambient, which may be efficiently detected by optical endpoint detection systems. Consequently, the corresponding etch process may be controlled on the basis of this endpoint detection signal in order to substantially completely remove the unwanted material of the layer 140, while not unduly removing any material of the silicon nitride layer 130.
Thereafter, the interlayer dielectric material 150 may be formed on the basis of well-established techniques followed by forming the resist mask 106. Next, an anisotropic etch process may be performed in which the layers 130, 140 may efficiently act as etch stop layers. In a subsequent etch process on the basis of a different etch chemistry, the layers 130 and 140 may be opened so as to provide an opening extending to the respective contact areas of the transistor elements. However, at areas in which an overlap of the two silicon nitride layers 130, 140 may occur, indicated as 152, the corresponding silicon dioxide layer 132 may not be efficiently removed during the etch step for etching through the material of the layer 150 in order to form a respective contact opening therein, such as the opening 151. Consequently, during the subsequent etch process for opening the silicon nitride material, the corresponding etch process encounters a layer stack comprised of nitride and oxide, which may result in a significantly different etch behavior compared to other areas in which a single nitride layer has to be opened. Consequently, the corresponding last process step for opening the nitride material may have a significantly increased complexity, thereby resulting in significant etch damage in areas having a single nitride layer or resulting in non-removed dielectric materials at the area 152. As a result, the conventional process strategy for forming silicon nitride layers of different intrinsic stress may yield respective non-uniformities, such as material residues 133 and/or contact non-uniformities caused by the complex layer stack at overlap regions 152, thereby also causing respective non-uniformities of the transistor performance.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.